# First Look at BFL’s ASIC Hardware

The last time I posted about anything related to Butterfly Labs appears to have been pretty controversial: for the first time in the short history of this little blog, I actually had to disable comments on a post, which didn’t really do much considering that my comments section was just the spill-over from the fighting happening on Reddit. I’ve been accused of actually being Sonny Vleisides, which makes that 3 hour Skype call I had with him seem like the most awkward descent into madness ever. Primarily, though, the place fingers get pointed most is the fact that almost none of what I was shown during that call to inspire my new-found confidence could be released. Well today I’ve been given the thumbs-up to release at least a bit of what I’ve learned. No doubt releasing product information before the manufacturer will only fan the flames for those convinced I’m a “paid shill” – I’ve never taken a penny from BFL, for any reason (though I’d totally trade ad space for ASICs, BFL or otherwise… Call me?) –  but if you want to see preliminary renderings of BFL’s new BitForce Single ‘SC’ I think you’ll set aside the conspiracy theory long enough to scroll down, yes?

Ladies and gentlemen, I present to you the Butterfly Labs BitForce Single ‘SC’

And in case you’re the sort who gets off on staring at PCB traces (we should start a club!) here’s the back side.

These images represent the first glimpse the public gets into the BitForce line. The board measures 92×92 mm and those 8 lovely chips in the center are the ASICs we’ve been talking so much about. As has been mentioned repeatedly in the various fight clubs strewn about the ‘net I am not an engineer, though I do carry at least some formal electronics training and quite a bit of hobby work – to that end, what I see in this board is perhaps more than what the average programmer would see, but I’m interested to see what the better-trained eyes of those more educated than myself make of it. See something interesting? Leave it in the comments – hopefully the bile levels will stay low enough that I can leave them open…

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1. Trippp says:

Thanks for providing these images. It looks like it's going to be a lot smaller than I thought it would be.

2. jimbit says:

Awsome!!!

3. Maybe my math is incorrect but how can 8 chips do 40 gh/s and 1 chip only does 3,5 gh/s (jalapeno)?

• Your math is right. There are a lot of theories floating around and while I do have an answer and it is forthcoming, it$’s not releasable information just yet. I$’ll say this though: To my knowledge, no one has guessed the answer to that one correctly yet… • Zba says: xxxxx5 chip does 4-ish-Ghash, xxxx10 chip does 8-ish-Ghash. 4-ish Ghash chip, could sustain 3.5 ghash easily while staying cool. Enter the Jally.. 8-ish-Ghash chip, run at a lower power/heat/safety overhead could sustain 5ghash easily. 8 x 5Ghash chip = 40 Ghash with room to spare, enter the SC. (also means that given enough power/heat/cooling/etc, one might actually see >40Ghash rates from an SC. <grin> ) • Like most of the theories this one is at least partially correct. Chips certainly vary in quality and the lower quality ones probably get binned for less taxing work, the Jalapeno does have heat and power constraints beyond those found in the Singles, but there's another important factor no one has guessed yet. It will all come out in due time :) • henkb52 says: Clear thanks for the answers, I think I'll just have to wait till mine comes in :-) • Ted Lynch says: So we know the Jally gives you 3.5G/Hash, while the single SC gives you 40G/Hash using 8 ASICs (equivalent to 5 G/Hash per ASIC). My guess would be the Jally has just a single ASIC running at a lower clock rate to ensure the temps and power demands are kept within spec. The production scaling means it must be the same ASIC*. Given the dimensions it could even be the same PCB as the SC, just minus the other 7 x ASICs. *The unlikley unknowns, and custom silicon is nowhere near my area of expertise, would be dual cores with only one running in the Jally and/or some parallel processing optimisation across cores, or even across n x ASICs, but I must confess I don't even know if the latter is even feasible. • MoonShad0w says: My guess is that the render we're seeing here is only half of an SC single. The newly-announced 30GH/s "little single" will be one board, and the standard-size 60GH/s single will be two in the same enclosure. 30GH/s / 8 ASICs = 3.75GH/s/ASIC, which is close to the original specs. I'm not sure of the details, but it seems that the Jalapenos are more stable at higher clocks than units containing more than one ASIC. If my guess is correct, this means it could be possible for "little singles" to reach 36GH/s, standard singles to reach 72GH/s, and MiniRigs (guessing 400 ASICs) to reach 1.8TH/s. 4. Zba says: My guesses on power usage: Jally : 18 watts SC : 200 watts MaxiRig : 5000 watt (Made up of 25-27 of the SC boards, MiniRig style) 5. Ted Lynch says: So, just how big will the Butterfly Effect be on the Bitcoin network? ;) Has anyone modelled it? 6. RHA says: 3.5 GH/s means probably one underclocked chip with simplified radiator (transferring the heat to the top of the case) and no fan. The temperature will be greater (especially with additional heater powered on) so the underclocking is a must. 7. Dookie says: Nice gate array! :) 8. is this for real? 9. obervator says: shipping november ? and anybody saw shots of the single sc ? • So far only pics of the board and renders of the enclosure, board and heatsink. No actual shots of the Single yet, but I\’m sure they\’re on their way soon. [/extract_itex$heading_3] Trackbacks

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